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⬢github C++ · 8 ★ +8 since we first saw it · pushed 3 h ago · NOASSERTION

FURSOY/fursoy-cpu

64-bit out-of-order superscalar RISC-V processor (RV64IMAFDV + Zba/Zbb) in SystemVerilog. Boots Linux 6.6.50 + BusyBox under Sv39 virtual memory and meets 500 MHz timing in Nangate 45nm.

Fursoy is a from-scratch 64-bit out-of-order, 2-wide superscalar RISC-V processor written in SystemVerilog, supporting RV64IMAFDV plus bit-manipulation extensions. It implements Sv39 virtual memory, full M/S/U privilege modes, and non-blocking caches, and can boot mainline Linux 6.6.50 with BusyBox. It's verified in simulation with Verilator and closes 500 MHz timing in open-source Nangate 45nm synthesis.

Why now: It was shared on Hacker News as a Show HN, highlighting that a solo SystemVerilog core can boot modern Linux with full out-of-order and vector support — notable in the RISC-V hobbyist/hardware community.

Who it is for: Hardware engineers, RISC-V enthusiasts, and students studying CPU microarchitecture or open-source silicon design.

risc-vsystemverilogcpuout-of-orderlinux-kernelopen-source-hardware

linux-kernelout-of-orderriscvsystemverilogverilator

Open on GitHub →

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