⬢github Verilog · 225 ★ +178 since we first saw it · pushed 31 min ago · Apache-2.0
FeSens/openTPU
An open-source AI accelerator, developed by AI: RTL, ISA, simulator, compiler and profiler in one repo. Runs Qwen3, LFM2.5 and Qwen3.5 on a Kintex-7 PCIe card.
openTPU is an open-source AI accelerator built largely by AI agents, shipped as a single readable monorepo containing the SystemVerilog RTL, instruction set, bit-exact simulator, compiler, and host software. It runs ten real models (Qwen3, LFM2.5, Gemma 4, SmolLM3, Phi-4-mini) with actual weights on a Kintex-7 FPGA PCIe card, producing tokens matching the simulator bit for bit.
Why now: It was discussed on Hacker News as evidence that AI can develop its own inference hardware — the chip that runs the models is designed by AI, closing a self-hosting loop that's a provocative milestone.
Who it is for: Developers and engineers who want to learn how AI accelerators work from Python matmul down to silicon, and anyone curious about AI-driven hardware design.
Stars over our 36 snapshots: 47 to 225, since 9 h ago.
Where people talked about it
- Yhn AI is now capable of developing its own inference hardware 13 min ago
- Mmastodon AI is now capable of developing its own inference hardware https://github.com/FeSens/openTPU # HackerNews # Tech # AI 6 h ago
API: https://socialmediatrends-api.osmike.com/v1/repos/FeSens/openTPU