⬢github Python · 587 ★ +14 since we first saw it · pushed 1 d ago · NOASSERTION
enjoy-digital/litedram
Small footprint and configurable DRAM core
LiteDRAM is a small, configurable FPGA DRAM controller core written in Python using Migen/LiteX. It supports SDR through DDR5 PHYs across Xilinx, Lattice, and Gowin devices, with AXI/Wishbone/Native interfaces, a crossbar frontend, DMA, BIST, and ECC. It can be used as a LiteX library or exported as Verilog for standard flows.
Why now: Mentioned on Hacker News in a discussion about DRAM interfaces and PHY tuning — why DDR3+ interfaces must be calibrated at boot.
Who it is for: FPGA/SoC engineers and open-source hardware developers who need memory controllers on Xilinx, Lattice, or Gowin FPGAs.
Stars over our 220 snapshots: 573 to 587, since 2 d ago.
Where people talked about it
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