RISC-V

A project called Qwenputer demonstrates a functioning, deterministic RISC-V CPU implemented inside Qwen3.5, showing that the model can simulate real processor behaviour rather than just generate text. The claim of deterministic execution is what is drawing attention, since large language models are usually probabilistic and prone to drift on long computations.

Russian semiconductor companies have shown off domestically developed CPU and SoC designs, demonstrating the silicon by running retro games. The designs include RISC-V and Arm-based processors alongside chips based on the Elbrus architecture. The display highlights Russia's push to build homegrown chip capability as Western sanctions restrict its access to foreign semiconductor technology.

Russian chipmakers demonstrated domestically produced RISC-V and Arm processors by running retro video games on them, including an NES clone operating on a Baikal microcontroller. The demos showcase Russia's push to build homegrown silicon amid Western export sanctions that have limited its access to foreign chips. Observers note the retro-game benchmarks underline both the progress and the modest performance level of current domestic designs.

A European RISC-V Industrial Computing Initiative has launched, aiming to advance open-standard RISC-V processor technology for industrial computing applications across Europe. The initiative, accessible at erici.eu, reflects growing European efforts to build sovereign, open-source hardware capabilities and reduce dependence on non-European chip architectures. Interest is concentrated among developers and hardware engineers following its announcement.

A developer has built a functioning RISC-V CPU simulation inside the Qwen3.5-4B language model, a project circulating among AI and hardware enthusiasts. The work suggests a large language model can emulate processor behavior, drawing interest from people following both open-source chip design and the limits of small open-weight models.

Alibaba's Damo Academy says more than 6 billion chips have now shipped using its XuanTie RISC-V architecture, according to the South China Morning Post. The figure underscores the growing adoption of the open RISC-V standard, which Chinese firms are embracing to reduce reliance on Western chip technologies such as Arm and x86 amid ongoing export restrictions.

An engineer has compiled a functional 32-bit RISC-V CPU directly into the weights of a Qwen 3.5 4B large language model, and used it to run the classic game DOOM. The unusual experiment blurs the line between neural networks and traditional computing hardware, and it is drawing attention for demonstrating that model weights can be made to behave like executable digital circuits.

Qualcomm has acquired Akeana, a startup that develops chips based on the open-source RISC-V architecture. The move signals Qualcomm's intent to expand beyond smartphones into AI accelerators and data-center processors, a market currently dominated by Nvidia, Intel and AMD. RISC-V is seen as a lower-cost, licensing-free alternative to Arm, making the deal notable for the industry's shift toward open chip designs.

Xinji Wuxian, a Chinese RISC-V chip designer with ties to Tsinghua University, has raised an early-stage venture capital round, according to Dealroom data. The funding underscores continued investor interest in RISC-V, an open-source chip architecture seen as a strategic alternative to Western-controlled designs amid tightening export controls on advanced semiconductors to China.

AI chip startup Tenstorrent, led by Jim Keller, has turned down acquisition offers from Intel and Qualcomm and instead raised $1.5 billion in new funding, choosing to stay independent. The company develops open-source RISC-V processors as an alternative to Nvidia's dominance in AI hardware. The move is drawing attention for its size and for the confidence it signals in competing with the major chipmakers.