Mmastodon Technology AI first seen 3 d ago, last 3 d ago, peak #4

Retro computer board's DRAM refresh design flaw examined

Original: And it caught onto a bit of design flaw: the board does the DRAM refreshes using full RAS+CAS read cycles instead of RAS

Enthusiasts are examining a design flaw in a vintage computer board: it performs DRAM refreshes using full RAS+CAS read cycles rather than RAS-only refresh cycles, simply not driving the data onto the system bus during refresh. While a read does refresh memory, making it functional, the approach is inefficient compared to the standard RAS-only method.

Why now: Technical retro-computing communities enjoy dissecting unusual or flawed hardware design choices in classic machines.

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Evidence

And it caught onto a bit of design flaw: the board does the DRAM refreshes using full RAS+CAS read cycles instead of RAS-only refresh cycles. It just doesn't push the data onto the system bus during a refresh. Which is fine, as far as it goes; a read will refresh the memory… · Hardhead13@mstdn.ca · 2

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