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Harmonic launches Aristotle formal verification for C and Verilog
Original: Aristotle: Formal Verification for C and Verilog
Harmonic has introduced Aristotle, a tool that applies formal verification to both C code and Verilog hardware descriptions. The system uses mathematical proofs to establish that software and hardware behave correctly, rather than relying on testing alone. Engineers and programmers are discussing the tool, with attention on what combining software and hardware verification in one system could mean for chip and safety-critical development.
Why now: Formal verification of both software and hardware is a notable technical step, and engineers are debating its practicality and implications.
Evidence
- Aristotle: Formal Verification for C and Verilog · jasondavies · 7
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